Internet Info 1993/Internet Info CD-ROM (Walnut Creek) (1993).iso/standards/ansi/X3T9/area13/cl_ata.txt

Text File | 1992-05-12 | 21.5 KB | 675 lines

Cirrus Logic, Inc., 7-11-89                                             Page

To:      Dal  Allan                                                     cc:
Gene Milligan
From:   Robert Kellert, Joe Chen
        Cirrus Logic, Inc., (408)-945-8300,     Fax: [phone]
Date:   11 July 1989

Re:      Suggested  Editorial Changes to the CAM Committee ATA  Proposal  Rev.
1.3, 14 June 1989



Overview


This  document points out areas of the ATA Proposed Specification that in  our
opinion  require  further clarification in the usual context  of  the  English
Language.  The  nature  of these changes  include  correction  of  grammatical
errors,  typographical  errors  and the addition of  text  to  add  consistent
definitions throughout the document. Proposed Functional and Electrical,  both
AC and DC, are not within the scope of this document.


Cirrus  Logic  views  that  ATA  interface is  a  40-pins  connector  and  its
associates which is used for command and data transfers in between peripherals
and AT bus.  This interface is based on the industrial de facto implementation
for the embedded devices utilize embedded controllers such as Cirrus Logic CL-
SH 260 AT/XT Disk Controller and its registers set.


------------------------------------------------------------------

3.  General Description

Break the sentence in the third Paragraph into two:

"The purpose of the ATA standard is to define a specification of the de  facto
implementations.   And  the  purpose  of  the  EATA  standard  is  to  provide
enhancement to the ATA interface which..."



3.1 Structure

The second paragraph does not list data transfer and its method, this sentence
should be rewrittern as follows:

"Also  defined are the method by which commands are directed  to  peripherals,
the contents of registers, and the method of data transfers."



4.1.1 ATA

The definition for ATA is not sufficient in describing the ATA is an interface
this document is trying to specified.  This paragraph should read:

"4.4.1 ATA (AT Bus Attachment): The interface derived from the original IBM PC
AT  rigid disk interface.  ATA contains a compatible register set to  the  IBM
interface  and  a  40-pins industrial de facto connector  and  its  associated
signals."



5.1 Configuration

The  third paragraph makes two references that constrict data transfer to  one
direction only. The third paragraph should be replaced as follows:

"Data is transferred in parallel (8 or 16 bits) either to or from host  memory
to  the drive's buffer under the direction of commands previously  transferred
from the host. The drive's controller performs all of the operations necessary
to  properly write data to, or read data from, the disk media. Data read  from
the media is stored in the drive's buffer pending transfer to the host  memory
and  data  is  transferred from the host memory to the drive's  buffer  to  be
written to the drive's media."



6.2.2 DD0-DD15

Change the paragraph to:

"An  8/16  bit  bi-directional data bus between the host  and  the  peripheral
devices.  The lower 8 bits of the data bus are used for registers, ECC  bytes,
and in case of IOCS16- is not asserted, an 8 bits data transfer.  All 16  bits
are used for data word transfer when IOCS16- is asserted."



6.2.3 DIOW-

This definition is incomplete and inconsistent with respect to the  definition
provided for DIOR- in 6.2.4. Section 6.2.3 should be changed as follows:

"Write  strobe, the rising edge of which clocks data from the host  data  bus,
DD0  through DD7 or DD0 through DD15, into a register or the data port of  the
drive."



6.2.9 PDIAG-

The  first sentence defines the signal but associates the signal as an  output
with the successful status indication. The first sentence should be changed as
follows:

"This  line  shall  be output by Drive 1 monitored by Drive 0  to  provide  an
indication of the results of a diagnostics command or a reset."



6.2.10 CS1FX- and 6.2.11 CS3FX-

These  two sections give identical vague definitions for two  unique  signals.
The sections should be written as follows:

"6.2.10 CS1FX-
This  is the chip select decoded from the host address bus used to select  the
host accessible Command Block Registers."

"6.2.11 CS3FX-
This  is the chip select decoded from the host address bus used to select  the
host accessible Control Block Registers."



6.2.12 DASP-

There is a grammatical error in the second paragraph. It should be reworded as
follows:

"Prior  to  the development of this standard, products were  introduced  which
asserted  DASP- when the drive was selected, and used it to drive an  activity
LED."



7.2 I/O Port Descriptions and Table 7-1

The  logic  conventions  of  Section 7.2 and the signal  names  of  Table  7-1
contradict  the  conventions  of  Section  6.1.  It  would  be  somewhat  more
consistent although not necessarily clearer if the signal headings in Table 7-
1 were succeeded with a (-) such as CS1FX- and CS3FX-.

The  register  count  and  listing as described  in  the  first  paragraph  is
incorrect. It should be changed as follows:

"Input and output to or from the drive is through an I/O Port that routes  the
input or output data to or from thirteen registers selected by a value on  the
CS1FX-,  CS3FX-, DA2, DA1, DA0, DIOR-, and DIOW- lines from the host. Nine  of
the  registers  are used for commands to the drive or status from  the  drive,



7.2.2 Error Register

Change TK0 to TK0NF to reflect the error status.

Move Table 7-5 of section 7.6.1 to this register description, define the  code
of this register in two modes: Operational Mode and Diagnostic Mode.



7.2.7 Cylinder High

Change the last sentence as follows:

"The most significant bits shall be loaded into the cylinder high register."



7.2.9 Status Register

The  BSY  bit  description  needs modification as  defined  in  the  following
sections:

"b) immediately upon host write of the command register."

The  "shared register" is not defined any where, replace the last sentence  of
BSY descriptions to:

"When BSY is asserted, any host read of a Command Block Register is  inhibited
and the status register is read instead."

Table 7-2: Command Codes and Parameters

Execute  Drive Diagnostic: The Drive Selection Parameter, "D", should  not  be
valid  for  this  command as both Drive 0 and Drive 1 must  respond.  The  "D"
should be changed to an "n".

Format   Track,   Write  Multiple,  and  Write  Sector(s):   The   PC   (Write
Precompensation register should not be listed as "n" for these commands. A new
code  "o"  for optional should be used since some drives still use  the  Write
Precompensation register as defined in Section 7.2.3.

SN is needed for translate mode calculation for the Seek command.



7.2.12 Digital Output

For editorial consistency, reverse the order of the IEN- bit description  with
the order of the SRST bit description.

Rename  the Digital Output register to Fixed Disk Control  register.   Digital
Output simply mis-lead the meaning of this register.

Remove  "enable"  descriptions  from the SRST, "enable" is  not  needed  after
reset.

The  last  paragraph  should  read as  follows  deleting  the  last  incorrect
sentence.

"- Unused bits are set to zero."



7.2.13 Drive Address

The last statement should read:

"When the host reads this register, bit 7 shall be in a high impedance state."



7.3 Reset Response

The first paragraph should remove the reference to re-enabling the drive as it
cannot be disabled.

"Once the reset has been removed, with BSY still asserted, ..."

Should  provide optional drive self diagnostic or test.  Remove last  part  of
the last sentence ", and no self test is performed"

Error register initial value should be 01 if no self diagnostic is  performed,
or should contain the error information if the self diagnostic is performed.



7.4.1 Error Reporting

Table 7-3:

ABRT error should not appears in Identify Drive and Recal commands.



7.5 Translate Mode

This  entire  paragraph  is  too  vague and devoid  of  any  real  content  to
contribute  anything  concrete  to the specification  and  should  be  removed
entirely.

TABLE 7-4: MANDATORY AND OPTIONAL COMMANDS

Format Desired track should be changed to Format Track as listed in Tables 7-2
and 7-3. Besides, I don't think anyone wants to format the Undesired track.



7.6.1 Execute Drive Diagnostic

Remove  2'nd  and 3'rd sentences of the first para. to provide  optional  self
diagnostic.

If Drive 1 is present:

Change the first statement to:

"- Drive 0 waits a minimum of 5 seconds before examine PDIAG- to allow Drive 1
post diagnostic result."

Change the second statement to:

"-  If Drive 1 negates PDIAG-, indicating a failure, Drive 0  shall  logically
"OR" x'80' with its own diagnostic status."

Change the forth statement to:

"If Drive 1 diagnostic failure is detected when drive 0 status is read,  Drive
1 status is obtained by setting the DRV bit after the BSY bit is deserted ..."

because if BSY is asserted, the Drive register can not be altered.

If there is no Drive 1 present:

The second sentence should be changed as follows:

"- Drive 0 negates BSY and generates an interrupt."

Last para., last sentence, "Drive 0 "ORs" x'00' with its own status" should be
stated: "Drive 0 posts its own status".

Reserve status code in Table 7-5, 06 to 7F.



7.6.2 Format Track

1'st  para.:  change "has been previously ..." to "is"  since  Set  Parameters
command is described later.

2,nd  para.,  2'nd sentence should not define format data, leave it  to  drive
specific.

2'nd para., 3'rd sentence should prefix with "For the physical mode,



7.6.4 Initialize Drive Parameters

Rewrite the 1'st sentence of the 2'nd para.:

"The  only  two registers values used by this command are  the  sector  number
register which the number of sector per track is specified, and the Drive/Head
register  where  the  number  of heads minus 1  is  specified.   The  DRV  bit
designates  these  values  to  the appropriate drive,  Drive  0  or  Drive  1,
respectively."



7.6.11 Set Buffer Mode Command

The  last sentence of the first paragraph is phrased with  grammatical  errors
making the intent incomprehensible. This sentence should be deleted.



7.6.12 Set Multiple Mode Command

The  first sentence of the second paragraph should be modified as follows  for
clarity:

"If the sector count register contains a valid value and ..."



7.6.14 Write Sector(s)

The first sentence of the first paragraph should be modified as follows:

"This  command writes from 1 to 256 sectors as specified in the  sector  count
register of the command block ..."

The second sentence of the fifth paragraph should be rewritten as follows:

"Upon  command completion, the command block registers contain  the  cylinder,
head, and sector number of the last sector written."



10.6 Command Protocol Timing

Because some of the driver may not read the status register, the interrupt can
be  cleared after the transfer complete to remove the interrupting  condition.
Rewrite  2'nd  para.  "thus interrupt shall not be  cleared  until  after  the
transfer  completes and the driver reads the status register." to define  host
interrupt set/reset conditions :

"thus  interrupt  can be cleared after the transfer completes, or  the  driver
reads  the  status register, or another command register  write  which  simply
starts another command cycle."





To:     Dal Allan
cc:     Gene Milligan
From:   Robert Kellert, Joe Chen
        Cirrus Logic, Inc, (408)-945-8300
Date:   11 July 1989

Re:      Suggested  Fuctional Changes to the CAM Committee ATA  Proposal  Rev.
1.3, 14 June 1989


The  following document lists items of a functional or electrical nature  that
must be considered for incorporation into the ATA proposed standard.

------------------------------------------------------------------

5.4 I/O Cable and Connector

To  ensure reliable operation, it is recommended that the third  paragraph  be
written as follows:

The maximum cumulative I/O cable length shall be 24 inches (0.61 meters).  The
DC Iol sink capability shall be 24 mA. The Ioh source capability shall be -400
uA. The capacitive loading Cl shall not exceed 200 pF.

TABLE 6-1 INTERFACE SIGNALS

Reserved  signals  shall be left unconnected at all connection points  of  the
cable.



6.2.5 DALE

This specification claims;

The  host address and chip selects, DA0 through DA2, CS1FX-, and  CS3FX-,  are
guaranteed on the falling edge of the signal.

The problem lies with the fact that address valid timing is not specified with
respect  to DALE in this document. System vendors need to provide a  value  of
address  valid to DALE falling such that the host bus adapter can  assure  the
chip selects are valid by the falling edge of DALE.



6.2.6 INTRQ

Add the following paragraphs:

"INTRQ is negated by the reset conditions such as assertion of RESET- line  or
writing  one  to bit 2 of the Fixed Disk register (Digital  Output  register).
This  signal is also cleared by the writing of the command register,  or  host
status register read, or optionally the transfer completes."

"INTRQ  is asserted at the beginning of each data block transfer,  ie.,  every
512  bytes  for non-multi block transfer or a multiple of 512  bytes  for  the
multi block  data transfers, the Read or Write Multiple commands.  There is an
exception to this condition, that is when host issues the "auto command", such
as  Format  Track, Write, Write Buffer, and Write Long, at  the  beginning  of
first block data transfer, INTRQ will no be asserted."



6.2.9 PDIAG-

This  signal shall be driven open collector and implement a load  resistor  on
each drive.

The  self  diagnostic should be provide at the power on or  reset.   And  this
diagnostic  is  a  device  specific implementation which may  not  be  in  all
devices.  In order to provide this option, the 3'rd sentence should be read:

"If the diagnostic is completed without error..."

Also, the last sentence should be changed to:

"...thus terminate the diagnostic"

Because DASP- can be implemented in firmware, the state of this signal may not
be  valid  until  the firmware detects command or  response  to  reset.   This
requires some delay before Drive 0 can examine the signal.  Add the  following
sentences to the paragraph:

"Drive  0  should  not  examine the PDIAG- within 500  ms  after  a  reset  or
diagnostic command to allow Drive 1 initialize this signal."



6.2.12 DASP-

The load resistors must be located on each drive.

Because DASP- can be implemented in firmware, the state of this signal may not
be  valid  until  the firmware detects command or  response  to  reset.   This
requires some delay before Drive 0 can examine the signal.  Add the  following
sentences before "At all time..."

"  Drive  0 should examine this signal by waiting minimum of 500  ms  after  a
reset  or diagnostic command to allow Drive 1 initialize this signal.   During
Drive Diagnostic, this line is driven by drive 0."



7.2 I/O Port Descriptions and Table 7-1

Table 7-1 should be listed with BSY and DREQ:

DREQ    BSY     CS1FX-CS3FX-DA2 DA1     DA0     IOR- assert     IOW- assert
------------------------------------------------------------------------------
---------------------------1     0       0      1        0       0       0
Read Data       Write Data
x       0       0       1       0       0       1       Error Status    Write
Precomp.
x       0       0       1       0       1       0       Sector Count    Sector
Count
x        0      0       1       0       1       1        Sector  NumberSector
Number
x         0      0       1       1       0       0       Cylinder   Low
Cylinder Low
x        0       0       1       1       0       1       Cylinder   High
Cylinder High
x         0       0      1       1        1       0       Drive/Head
Drive/Head
x          0      0       1       1       1       1        Status
Command
x          1      0       1       1       1       1        Status
Invalid
x       x       1       0       1       1       0       Alt. Status      Fixed
Disk
x        x       1       0       1       1       1       Digital   Input
Reserved
------------------------------------------------------------------------------
---------------------------



7.2.4 Sector Count

"The  sector  count defines the number of sectors of data  to  be  transferred
across the host bus for the subsequent command. If the value in this  register
is  zero,  a count of 256 sectors is specified. The count is  decremented  for
each sector successfully transferred between the host and drive.

At  command completion, this value is zero if the command was successful.  The
value  is  changed to the remaining number of sectors left to  read  from  the
drive or write to the drive if an error occurred during a multi-sector command
operation.

The  contents  of this register define the number of sectors  per  track  when
executing an Initialize Drive Parameters or Format Track command."



7.2.5 Sector Number

"This  register contains the starting sector number for any disk  data  access
for the subsequent command. Sector number starts from 1 to the maximum  number
of sector per track, a value of zero is not a valid sector number."

The  sector  number is incremented for each  sector  successfully  transferred
between  the host and drive. At command completion the value is one  plus  the
last sector number accessed modulo the number of sectors per track. The sector
number  is changed to the sector number at which an error occurred for  multi-
sector operations."



7.2.9 Status register

- ERR: add the following

"The error bit is automatically cleared by a command load."



7.2.10 Command register

Reserve command code 00h, this command code should not be used.



10.4 Timing

T6 should be 0 ns min.




To:     Dal Allan
cc:     Gene Milligan
From:   Robert Kellert, Joe Chen
        Cirrus Logic, Inc., (408)-945-8300
Date:   11 July 1989

Re:      Suggested Functional Enhancements to the CAM Committee  ATA  Proposal
Rev. 1.3, 14 June 1989




This  document  describes  two  major  functional  enhancements  to  the   ATA
interface: 1). The I/O wait mechanism for the synchronization of the host  and
device  data  transfer, and 2). The DMA data transfer  implementation  on  the
interface.  These enhancements provide additional functions as to matching the
system and device speed, and to allow multi-tasking host driver.  In addition,
it  is backward compatible with current hardware and software (system  driver)
implementation.

The  requuirements of this enhanment are to define three more signals  at  the
40-pins  connector:  IOCHRDY-, DREQ, and DACK-, and bit 0 of  the  Fixed  Disk
register.   The  following section describes the  implementation  that  Cirrus
Logic current support.


------------------------------------------------------------------

6.1 Signal Summary

Add  IOCHRDY-,  DREQ,  and DACK- to table 6-1, the pin  assignment  is  to  be
defined.

6.2.13 IOCHRDY- (I/O Channel Ready)

Add  this  section to provide a automatic I/O wait state generation,  for  the
matching speed of the host and the device.  The signal was designed in the  AT
interface for variety of I/O devices.

"This  signal  is asserted to extend host transfer cycle when  the  peripheral
device  is not ready to respond a data transfer, such as data read  or  write.
The timing of this signal is in section X.X.X"



6.2.14 DREQ (DMA Request)

This  section and DACK- is to provide DMA transfer at the ATA  interface.  Add
the following paragraphs to the document.

"This  signal  is used for the DMA data transfer between host  and  peripheral
devices.  The signal is driven by the device when it is ready to write or read
data to or from the host.  The direction of data transfer is controlled by the
IOR-  and IOW-.  The DREQ and DACK- signals provide a means of  DMA  handshake
between  the  host and peripheral devices.  Device asserting  DREQ  will  wait
until  host  asserts  DACK- before deserting itself and  continuing  the  next
transfer  period.   The DREQ/DACK- handshake will be continued until  all  the
data  transfer finished.  The timing of DREQ, DACK- and Data Bus is  described
in section X.X.X."

Bit  0 of the 'Digital Output Register' (AT Host Fixed Disk Control  Register)
enables the AT DMA transfer at the interface.  When this bit is asserted,  the
DMA  data transfer is enabled, and data is handshaked by  DREQ/DACK-  signals.
Data  transfer  can be either 8 bits or 16 bits depend upon  the  IOCS16-,  by
convention, the ECC bytes are transferred by 8 bit data."



6.2.15 DACK- (DMA Acknowledge)

Add this section as:

"This  signal  is used for the host to response DREQ for  DMA  transfer.   The
timing  of  DREQ,  DACK-  and Data Bus is described  in  section  X.X.X.   DMA
transfer is used in data transfer only."



7.2.1 Data Port

Change the sentence "All Transfers are high speed..." to:

"Data transfer can be synchronous PIO or asynchronous DMA transfer, the  width
of data bus is depended upon the signal IOCS16-.  Data transfer for ECC  bytes
of Read Long and Write Long are 8 bits wide."



7.2.12 Fixed Disk (Digital Output)

Add DMAEN at bit 0 of this register:

"- DMAEN is an optional bit to support DMA transfer through the ATA interface.
When  this  bit  is asserted, the data transfer between  host  and  device  is
handshaked  by the DREQ and DACK- signals at the interface.  Data transfer  on
the bus can be either 8 bits or 16 bits depending upon IOCS16-."



10.4 Timing

Add DMA timing.

Add IOCHRDY- timing.









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        IBM is a registered trademark of International Business Machine